1. Field of the Invention
The present invention relates to a shift register and an organic light emitting display device using the same, and more particularly, to a shift register capable of reducing power consumption and an organic light emitting display device using the same.
2. Discussion of Related Art
An organic light emitting display device is a flat panel display (FPD) that displays an image using organic light emitting diodes (OLEDs) that generate light by re-combination of electrons and holes. The organic light emitting display device has a high response speed and is driven with low power consumption. In a conventional organic light emitting display device, currents corresponding to data signals are supplied to OLEDs using driving transistors formed in pixels, respectively, so that light is generated by the OLEDs.
The above-described conventional organic light emitting display device includes a data driver for supplying data signals to data lines, a scan driver for supplying (or sequentially supplying) scan signals to scan lines, and a display region including a plurality of pixels connected to the data lines and the scan lines.
The pixels included in the display region are selected when the scan signals are supplied to the scan lines to receive the data signals from the data lines. The pixels that received the data signals generate light components of a certain (or predetermined) brightness corresponding to the data signals to display a certain (or predetermined) image. In the conventional organic light emitting display device, the scan driver includes a plurality of stages in order to generate (or sequentially generate) the scan signals.
FIG. 1 schematically illustrates a shift register of a conventional scan driver.
Referring to FIG. 1, the shift register of the conventional scan driver includes stages 2a, 2b, 2c, 2d, . . . for supplying (or sequentially supplying) scan signals to a plurality of scan lines S1, S2, S3, S4, . . . ; NAND gates NAND1, NAND2, NAND3, NAND4, . . . serially connected between the output ports of the stages 2a, 2b, 2c, 2d, and the scan lines S1, S2, S3, S4, . . . ; and inverters IN1, IN2, IN3, IN4, . . . .
Each of the stages 2a, 2b, 2c, 2d, . . . receives a clock signal Clk and a clock bar signal (or an inverse clock signal) /Clk supplied from an external source. Each of the stages 2a, 2b, 2c, 2d, . . . that received the clock signal Clk and the clock bar signal /Clk generates a sampling pulse when a sampling pulse or a start pulse SP is supplied from a previous stage to supply the generated sampling pulse to each of the NAND gates NAND1, NAND2, NAND3, NAND4, . . . . The NAND gates NAND1, NAND2, NAND3, NAND4, . . . perform a NAND operation using the output signals of a current stage and a next stage to supply the NAND operation results to the inverters IN1, IN2, IN3, IN4, . . . . Then, the inverters IN1, IN2, IN3, IN4, . . . invert the outputs of the NAND gates NAND1, NAND2, NAND3, NAND4, . . . to supply the inverted outputs to the scan lines S1, S2, S3, S4, . . . .
FIG. 2 is a circuit diagram illustrating the stages illustrated in FIG. 1 in more detail. In FIG. 2, for convenience purposes, the first and second stages 2a and 2b are illustrated.
Referring to FIG. 2, each of the first and second stages 2a and 2b includes a first inverter 2a1 or 2b1 for receiving a start pulse SP or a sampling pulse, a second inverter 2a2 or 2b2 for inverting the output of the first inverter 2a1 or 2b1, and a third inverter 2a3 or 2b3 for feeding back the output of the second inverter 2a2 or 2b2 to the input of the second inverter 2a2 or 2b2.
The first inverter 2a1 or 2b1 is synchronized with the clock signals Clk and /Clk when the start pulse SP or the sampling pulse is supplied in order to output a logic (or predetermined logic) signal.
The second inverter 2a2 or 2b2 inverts the logic signal supplied from the first inverter 2a1 or 2b1 to generate a sampling pulse SP1 or SP2. Here, the first sampling pulse SP1 generated by the second inverter 2a2 included in the first stage 2a is supplied to the first NAND gate NAND1 and the second stage 2b.The second sampling pulse SP2 generated by the second inverter 2a2 included in the second stage 2b is supplied to the second NAND gate NAND2 and the third stage 2c. 
The third inverter 2a3 or 2b3 inverts the sampling pulse SP1 or SP2 of the second inverter 2a2 or 2b2 to supply the inverted sampling pulse SP1 or SP2 to the input terminal of the second inverter 2a2 or 2b2. That is, the third inverter 2a3 or 2b3 assists in stably generating the sampling pulse SP1 or SP2 of the second inverter 2a2 or 2b2.
The first NAND gate NAND1 performs a NAND operation using the sampling pulses SP1 and SP2 output from the first and second stages 2a and 2b to supply the NAND operation result to the inverter IN1. Then, the inverter IN1 inverts the output of the first NAND gate NAND1 to supply the inverted output to the scan line S1.
The operations of the conventional stages 2a and 2b will be described in more detail with reference to the waveforms of FIG. 3.
First, the clock signal Clk and the clock bar signal /Clk are supplied from the external source to the stages 2a, 2b, . . . , respectively. The start pulse SP is supplied from an external source to the first stage 2a. Then, the first inverter 2a generates an output signal at a low level when the clock signal Clk at a high level and the clock bar signal /Clk at a low level are input. Here, the output signal at the low level is transited to a high level when the supply of the start pulse SP is stopped and the clock signal Clk at the high level and the clock bar signal /Clk at the low level are input. The output of the first inverter 2a1 is inverted by the second inverter 2a2. That is, the second inverter 2a2 inverts the output of the first inverter 2a1 to generate the first sampling pulse SP1. The first sampling pulse SP1 generated by the second inverter 2a2 is supplied to the second stage 2b and the first NAND gate NAND1.
The first inverter 2b1 of the second stage 2b that received the first sampling pulse SP1 generates an output signal at a low level when the clock signal Clk at the low level and the clock bar signal /Clk at the high level are input. Here, the output signal at the low level is transited to a high level when the supply of the first sampling pulse SP1 is stopped and the clock signal Clk at the low level and the clock bar signal /Clk at the high level are input. The output of the first inverter 2b1 is inverted by the second inverter 2b2. That is, the second inverter 2b2 inverts the output of the first inverter 2b1 to generate the second sampling pulse SP2. The second sampling pulse SP2 generated by the second inverter 2b2 is supplied to the third stage 2c and the second NAND gate NAND2.
On the other hand, the first NAND gate NAND1 outputs a low level signal only when the first and second sampling pulses SP1 and SP2 are simultaneously supplied and outputs a high level signal in other cases. The inverter IN1 inverts the output of the first NAND gate NAND1 to generate a scan signal and supplies the generated scan signal to the scan line S1. Alternatively, in accordance with the structure of a pixel of an alternative embodiment the output of the first NAND gate NAND1 may be directly supplied to the scan line S1.
In a conventional art, the above-described processes are repeated to sequentially supply the scan signals to the scan lines S1, S2, . . . . However, the conventional scan driver consumes a large amount of power due to high capacitance generated during the input of the clock signal Clk and the clock bar signal /Clk. That is, in the conventional art, the clock signal Clk and the clock bar signal /Clk are supplied to the stages 2a, 2b, . . . , respectively. Here, a capacitance (or a predetermined capacitance) is generated in the part where the signal lines overlap with each other when the clock signal Clk and the clock bar signal /Clk are supplied and increases power consumption.
Also, in the conventional art, the clock signal Clk and the clock bar signal /Clk are directly input to the first inverters 2a1, 2b1, . . . and the third inverters 2a3, 2b3, . . . included in the stages 2a, 2b, . . . , respectively. The clock signal Clk and the clock bar signal /Clk are directly input to the gate terminals of the transistors that constitute the first inverters 2a1, 2b1, . . . and the third inverters 2a3, 2b3, . . . . Here, the gate terminals of the transistors have high capacitance. Therefore, when the clock signal Clk and the clock bar signal /Clk are directly input to the gate terminals of the transistors that constitute the first inverters 2a1, 2b1, . . . and the third inverters 2a3, 2b3, . . . , power consumption increases due to the high capacitance. In particular, since the clock signal Clk and the clock bar signal /Clk are supplied to all of the stages 2a, 2b, . . . , regardless of the driving of the stages 2a, 2b, . . . , the capacitance generated by the first inverters 2a1, 2b1, . . . and the third inverters 2a3, 2b3, . . . increases to thereby increase power consumption.
On the other hand, in the conventional art, in order to reduce the capacitance applied to the clock signal Clk and the clock bar signal /Clk, switches are added before the stages 2a, 2b, . . . , respectively, and the added switches are turned on during driving. However, in the above-described method, since the stages 2a, 2b, are floated when the switches are turned off, driving is not stably performed.